Silicon carbide (SiC) has a broader band gap and a higher dielectric breakdown voltage than silicon (Si), and therefore, is expected to be the best semiconductor material to make a next-generation low-loss power device. SiC has a lot of poly-types including cubic ones such as 3C—SiC and hexagonal ones such as 6H—SiC and 4H—SiC. Among these various poly-types, the one that is used generally to make a practical silicon carbide semiconductor element is 4H—SiC.
Among various power devices that use SiC, field effect transistors such as a metal-insulator-semiconductor field effect transistor (which will be referred to herein as a “MISFET”) and a metal-semiconductor field effect transistor (which will be referred to herein as a “MESFET”) are known as typical switching elements. Such a switching element can switch between ON state in which drain current of several amperes (A) or more flows and OFF state in which the drain current becomes zero by changing the voltage applied to between its gate and source electrode. Also, in the OFF state, such a switching element will achieve as high a breakdown voltage as several hundred volts or more. As for rectifiers, a Schottky diode, a pn diode and other SiC rectifiers have already been reported and are all expected to be rectifiers that can operate with a huge amount of current and with a high breakdown voltage.
SiC has a higher dielectric breakdown voltage and a higher thermal conductivity than Si. That is why a power device that uses SiC (which will be referred to herein as a “SiC power device”) can have a higher dielectric strength and will cause smaller loss than a Si power device. That is why if a SiC power device can have as high performance as a Si power device, the SiC power device can have much smaller area and thickness than the Si power device.
To make an even larger amount of current flow through a power device such as a MISFET, it is effective to increase the channel density. For that reason, a vertical power MISFET with a trench gate structure has been proposed as a replacement for a traditional planar gate structure. In the planar gate structure, a channel region is defined on the surface of a semiconductor layer. In the trench gate structure, on the other hand, a channel region is defined on the side surface of a trench that has been formed in a semiconductor layer.
Hereinafter, a cross-sectional structure of a vertical MISFET with the trench gate structure will be described with reference to the accompanying drawings. The vertical MISFET ordinarily has a plurality of unit cells that are arranged two-dimensionally. Each of those unit cells has a trench gate.
FIG. 10 is a cross-sectional view illustrating one cell pitch (i.e., a single unit cell) of a traditional vertical MISFET 1000 with the trench gate structure. In the example illustrated in FIG. 10, each unit cell has a trench gate, of which a side surface is substantially perpendicular to the principal surface of the substrate.
The vertical MISFET 1000 includes a substrate 1 of silicon carbide and a silicon carbide layer 2 that has been formed on the principal surface of the silicon carbide substrate 1. The silicon carbide layer 2 includes an n-type drift region 2d that has been defined on the principal surface of the silicon carbide substrate 1 and a p-type body region 3 that has been defined on the drift region 2d. An n-type source region 4 forms part of the surface region of the body region 3. A trench 5 has been formed in the silicon carbide layer 2 so as to run through the body region 3 and reach the drift region 2d. In this example, the trench 5 has a side surface that is perpendicular to the principal surface of the substrate 1. Inside of the trench 5, arranged are a gate electrode 7 and a gate insulating film 6 that insulates the gate electrode 7 from the silicon carbide layer 2. Further arranged on the silicon carbide layer 2 is a source electrode 10 that contacts with the source region 4 and a body region 3. And a drain electrode 9 is arranged on the back surface of the silicon carbide substrate 1.
A vertical MISFET like this may be fabricated in the following manner.
First of all, on the principal surface of an n-type silicon carbide substrate 1 with low resistivity, formed is a silicon carbide layer 2 having the same crystal structure as the silicon carbide substrate 1. For example, an n-type drift region 2d and a p-type body region 3 are defined in this order by epitaxial growth process on the principal surface of the silicon carbide substrate 1, thereby obtaining a silicon carbide layer 2. After that, a mask layer (not shown) of silicon dioxide is put on a predetermined area of the silicon carbide layer 2 and used as a mask through which n-type dopant ions (such as N (nitrogen) ions) are implanted into the body region 3, thereby defining a source region 4 in the body region 3.
After the mask has been removed, an Al film (not shown) is deposited on a part of the source region 4 with an oxide film interposed between them, and used as a mask, through which a trench 5 is cut to reach the drift region 2d. 
Next, a gate insulating film 6 and a gate electrode 7 are formed in this order inside of the trench 5. The gate insulating film 6 may be an oxide film, which is obtained by thermally oxidizing the silicon carbide layer 2.
The gate electrode 7 may be formed 6 by depositing polysilicon on the gate insulating film 6 by low pressure chemical vapor deposition (LP-CVD) process and then patterning it, for example. Meanwhile, a source electrode 10 is formed on the silicon carbide layer 2 to cover both the body region 3 and the source region 4, while a drain electrode 9 is formed on the back surface of the silicon carbide substrate 1. In this manner, a vertical MISFET with a trench gate structure is completed.
In a MISFET with such a trench gate structure, when the source electrode 10 and the gate electrode 7 are both grounded or when a negative bias voltage is applied to the gate electrode 7, holes are induced and stored in the vicinity of the interface between the body region 3 and the gate insulating film 6 in the region between the source region 4 and the drift region 2d, and the path of electrons which are conduction carriers is cut off. As a result, no current flows (i.e., the MISFET turns OFF). In this case, if a high voltage is applied to between the drain electrode 9 and the source electrode 10 so that the drain electrode 9 has positive potential, then the PN junction between the body region 3 and the drift region 2d becomes reverse biased. As a result, a depletion layer expands in the body region 3 and in the drift region 2d and a high voltage can be maintained.
On the other hand, if a positive bias voltage that is equal to or higher than a threshold voltage is applied to the gate electrode 7, electrons are induced and inverted in the vicinity of the interface between the body region 3 and the gate insulating film 6 in the region between the source region 4 and the drift region 2d, and an inversion layer is formed there. As a result, carriers flow from the source electrode 10 toward the drain electrode 9 by way of the source region 4, the inversion layer (not shown) that that has been formed in the body region 3 and that contacts with the gate insulating film 6, the drift region 2d and the silicon carbide substrate 1. That is to say, the MISFET turns ON.
In a vertical MISFET with the planar structure, a junction field effect transistor (which will be abbreviated herein as “JFET”) is formed as a parasitic transistor between adjacent unit cells and produces a resistive component (JFET resistance). This JFET resistance is produced when current flows through the drift region that is interposed between adjacent body regions. The narrower the interval between those unit cells (i.e., the narrower the gap between the adjacent body regions), the greater the JFET resistance. That is why if the cell pitch is reduced to cut down the size, the ON-state resistance increases as the JFET resistance rises.
On the other hand, since the MISFET 1000 with the trench gate structure has no JFET resistance, the ON-state resistance decreases monotonically as the cell pitch is reduced, which is beneficial. For that reason, to cut down the size of a unit cell, it is more advantageous to adopt a MISFET with the trench gate structure.
However, in a MISFET 1000 with such a trench gate structure, the gate insulating film 6 on the inner wall of the trench 5 may have its reliability decreased due to some damage or contamination inside the trench 5, which is a problem. In addition, since the electric field intensity easily becomes excessively high at a corner portion 5A at the rim of the trench 5 and at a corner portion 5B at the bottom of the trench 5, a decrease in the breakdown voltage of the device could be caused.
To overcome such a problem, people proposed a method for smoothing and rounding such corner portions of the trench 5 by cutting the trench through a silicon carbide layer by dry etching and then conducting a heat treatment process (see Patent Document No. 1, for example). In this description, “to round” means turning a corner portion (such as a corner or an edge) into a rounder shape. Furthermore, other people proposed embedding an SiO2 film on the bottom of a trench in order to secure an even higher breakdown voltage at the bottom of the trench (see Patent Document No. 2, for example).